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differential/single-ended input, dual 1 msps, 12-bit, 3-channel sar adc ad7265 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features functional block diagram 12-bit successive approximation adc d out a output drivers control logic t/h buf v a1 v a2 v a3 v a4 v a5 v a6 mux ref ad7265 v drive ref select d cap a av dd dv dd buf d out b output drivers 12-bit successive approximation adc t/h v b1 v b2 v b3 v b4 v b5 v b6 mux agnd agnd agnd d cap b dgnd dgnd cs sclk range sgl/diff a0 a1 a2 04674-001 dual 12-bit, 3-channel adc throughput rate: 1 msps specified for v dd of 2.7 v to 5.25 v power consumption 7 mw at 1 msps with 3 v supplies 17 mw at 1 msps with 5 v supplies pin-configurable analog inputs 12-channel single-ended inputs 6-channel fully differential inputs 6-channel pseudo differential inputs 70 db sinad at 50 khz input frequency accurate on-chip reference: 2.5 v 0.2% maximum @ 25c, 20 ppm/c maximum dual conversion with read 875 ns, 16 mhz sclk high speed serial interface spi?-/qspi?-/microwire?-/dsp-compatible ?40c to +125c operation shutdown mode: 1 a maximum 32-lead lfcsp and 32-lead tqfp 2 msps version, ad7266 general description figure 1. the ad7265 1 is a dual, 12-bit, high speed, low power, successive approximation adc that operates from a single 2.7 v to 5.25 v power supply and features throughput rates of up to 1 msps. the device contains two adcs, each preceded by a 3-channel multiplexer, and a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 30 mhz. product highlights 1. two complete adc functions allow simultaneous sampling and conversion of two channels. each adc has three fully/pseudo differential pairs, or six single-ended channels, as programmed. the conversion result of both channels is simultaneously available on separate data lines, or in succession on one data line if only one serial port is available. the conversion process and data acquisition use standard control inputs allowing easy interfacing to microprocessors or dsps. the input signal is sampled on the falling edge of cs ; conversion is also initiated at this point. the conversion time is determined by the sclk frequency. the ad7265 uses advanced design techniques to achieve very low power dissipation at high throughput rates. with 5 v supplies and a 1 msps throughput rate, the part consumes 4 ma maximum. the part also offers flexible power/throughput rate management when operating in normal mode, because the quiescent current consumption is so low. 2. high throughput with low power consumption. the ad7265 offers a 1 msps throughput rate with 9 mw maximum power dissipation when operating at 3 v. 3. the ad7265 offers both a standard 0 v to v ref input range and a 2 v input range. ref 4. no pipeline delay. the part features two standard successive approximation adcs with accurate control of the sampling instant via a the analog input range for the part can be selected to be a 0 v to v cs input and once off conversion control. (or 2 v ref ref ) range, with either straight binary or twos complement output coding. the ad7265 has an on-chip 2.5 v reference that can be overdriven when an external reference is preferred. this external reference range is 100 mv to v 1 protected by u.s. patent no. 6,681,332. dd . the ad7265 is available in 32-lead lfcsp and 32-lead tqfp.
ad7265 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 9 ter mi nolo g y .................................................................................... 11 theory of operation ...................................................................... 13 circuit information .................................................................... 13 converter operation .................................................................. 13 analog input structure .............................................................. 13 analog inputs .............................................................................. 14 analog input selection .............................................................. 17 output coding ............................................................................ 17 transfer functions ...................................................................... 18 digital inputs .............................................................................. 18 v drive ............................................................................................ 18 modes of operation ....................................................................... 19 normal mode .............................................................................. 19 partial power-down mode ....................................................... 19 full power-down mode ............................................................ 20 power-up times ......................................................................... 21 power vs. throughput rate ....................................................... 21 serial interface ................................................................................ 22 microprocessor interfacing ........................................................... 23 ad7265 to adsp218x ............................................................... 23 ad7265 to adsp-bf53x ........................................................... 24 ad7265 to tms320c541 .......................................................... 24 ad7265 to dsp563xx ................................................................ 25 application hints ........................................................................... 26 grounding and layout .............................................................. 26 pcb design guidelines for lfcsp .......................................... 26 evaluating the ad7265 performance ...................................... 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 11/06rev. 0 to rev. a changes to format .............................................................universal changes to reference input/output section ................................ 4 changes to table 4............................................................................ 7 changes to terminology section.................................................. 11 changes to figure 24 and differential mode section................ 15 changes to figure 29...................................................................... 16 changes to ad7265 to adsp-bf53x section............................. 24 updated outline dimensions ....................................................... 27 changes to ordering guide .......................................................... 27 4/05revision 0: initial version
ad7265 rev. a | page 3 of 28 specifications t a = t min to t max , v dd = 2.7 v to 5.25 v, f sclk = 16 mhz, f s = 1 msps, v drive = 2.7 v to 5.25 v; specifications apply using internal reference or external reference = 2.5 v 1%, unless otherwise noted. 1 table 1. parameter specification unit test conditions/comments dynamic performance signal-to-noise ratio (snr) 2 71 db min f in = 50 khz sine wave; differential mode 69 db min f in = 50 khz sine wave; single-ended and pseudo differential modes signal-to-noise + distortion ratio (sinad) 2 70 db min f in = 50 khz sine wave; differential mode 68 db min f in = 50 khz sine wave; single-ended and pseudo differential modes total harmonic distortion (thd) 2 C77 db max f in = 50 khz sine wave; differential mode C73 db max f in = 50 khz sine wave; single-ended and pseudo differential modes spurious-free dynamic range (sfdr) 2 C75 db max f in = 50 khz sine wave intermodulation distortion (imd) 2 fa = 30 khz, fb = 50 khz second-order terms C88 db typ third-order terms C88 db typ channel-to-channel isolation C88 db typ sample and hold aperture delay 3 11 ns max aperture jitter 3 50 ps typ aperture delay matching 3 200 ps max full power bandwidth 33/26 mhz typ @ 3 db, v dd = 5 v/v dd = 3 v 3.5/3 mhz typ @ 0.1 db, v dd = 5 v/v dd = 3 v dc accuracy resolution 12 bits integral nonlinearity 2 1 lsb max 0.5 lsb typ; differential mode 1.5 lsb max 0.5 lsb typ; single-ended and pseudo differential modes differential nonlinearity 2 , 4 0.99 lsb max differential mode ?0.99/+1.5 lsb max single-ended and pseudo differential modes straight binary output coding offset error 6 lsb max offset error match 2 lsb typ gain error 2.5 lsb max gain error match 0.5 lsb typ twos complement output coding positive gain error 2 lsb max positive gain error match 0.5 lsb typ zero code error 5 lsb max zero code error match 1 lsb typ negative gain error 2 lsb max negative gain error match 0.5 lsb typ analog input t 5 single-ended input range 0 v to v ref v range pin low 0 v to 2 v ref range pin high pseudo differential input range: v in+ ? v in? 6 0 to v ref v range pin low 2 v ref v range pin high fully differential input range: v in+ and v in? v cm v ref /2 v v cm = common-mode voltage 7 = v ref /2 v in+ and v in? v cm v ref v v cm = v ref
ad7265 rev. a | page 4 of 28 parameter specification unit test conditions/comments dc leakage current 1 a max input capacitance 45 pf typ when in track 10 pf typ when in hold reference input/output reference output voltage 8 2.5 v min/v max 0.2% max @ 25c long-term stability 150 ppm typ for 1000 hours output voltage hysteresis 2 50 ppm typ reference input voltage range 0.1/v dd v min/v max see typical performance characteristics section dc leakage current 2 a max external reference applied to pin d cap a/pin d cap b input capacitance 25 pf typ d cap a, d cap b output impedance 10 typ reference temperature coefficient 20 ppm/c max 10 ppm/c typ v ref noise 20 v rms typ logic inputs input high voltage, v inh 2.8 v min input low voltage, v inl 0.4 v max input current, i in 15 na typ v in = 0 v or v drive input capacitance, c in 3 5 pf typ logic outputs output high voltage, v oh v drive ? 0.2 v min output low voltage, v ol 0.4 v max floating state leakage current 1 a max floating state output capacitance 3 7 pf typ output coding straight (natural) binary sgl/ diff = 1 with 0 v to v ref range selected twos complement sgl/ diff = 0; sgl/ diff = 1 with 0 v to 2 v ref range conversion rate conversion time 14 sclk cycles 875 ns with sclk = 16 mhz track-and-hold acquisition time 3 90 ns max full-scale step input; v dd = 5 v 110 ns max full-scale step input; v dd = 3 v throughput rate 1 msps max power requirements v dd 2.7/5.25 v min/v max v drive 2.7/5.25 v min/v max i dd digital i/ps = 0 v or v drive normal mode (static) 2.3 ma max v dd = 5.25 v operational, f s = 1 msps 4 ma max v dd = 5.25 v; 3.5 ma typ f s = 1 msps 3.2 ma max v dd = 3.6 v; 2.7 ma typ partial power-down mode 500 a max static full power-down mode (v dd ) 1 a max t a = ?40c to +85c 2.8 a max t a > 85c to 125c power dissipation normal mode (operational) 21 mw max v dd = 5.25 v partial power-down (static) 2.625 mw max v dd = 5.25 v full power-down (static) 5.25 w max v dd = 5.25 v, t a = ?40c to +85c 1 temperature range is ?40c to +125c. 2 see terminology section. 3 sample tested during initial release to ensure compliance. 4 guaranteed no missed codes to 12 bits. 5 v in ? or v in+ must remain within gnd/v dd . 6 v in? = 0 v for specified performance. for full input range on v in? pin, see figure 28 and figure 29. 7 for full common-mode range, see figure 24 and figure 25. 8 relates to pin d cap a or pin d cap b.
ad7265 rev. a | page 5 of 28 timing specifications av dd = dv dd = 2.7 v to 5.25 v, v drive = 2.7 v to 5.25 v, internal/external reference = 2.5 v, t a = t max to t min , unless otherwise noted 1 . table 2 . parameter limit at t min , t max unit description f sclk 2 1 mhz min t a = ?40c to +85c 4 mhz min t a > 85c to 125c 16 mhz max t convert 14 t sclk ns max t sclk = 1/f sclk 875 ns max f sclk = 16 mhz t quiet 30 ns min minimum time between end of serial read and next falling edge of cs t 2 15/20 ns min v dd = 5 v/3 v, cs to sclk setup time, t a = ?40c to +85c 20/30 ns min v dd = 5 v/3 v, cs to sclk setup time, t a > 85c to 125c t 3 15 ns max delay from cs until d out a and d out b are three-state disabled t 4 3 36 ns max data access time after sclk falling edge, v dd = 3 v 27 ns max data access time after sclk falling edge, v dd = 5 v t 5 0.45 t sclk ns min sclk low pulse width t 6 0.45 t sclk ns min sclk high pulse width t 7 10 ns min sclk to data valid hold time, v dd = 3 v 5 ns min sclk to data valid hold time, v dd = 5 v t 8 15 ns max cs rising edge to d out a, d out b, high impedance t 9 30 ns min cs rising edge to falling edge pulse width t 10 5 ns min sclk falling edge to d out a, d out b, high impedance 50 ns max sclk falling edge to d out a, d out b, high impedance 1 sample tested during initial release to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. all timing specifications given are with a 25 pf load capacitance. with a load capacitance greater than this value, a digital b uffer or latch must be used. see the serial interface section and figure 41 and figure 42. 2 minimum sclk for specified performance ; with slower sclk frequencies, perfor mance specifications apply typically. 3 the time required for the output to cross 0.4 v or 2.4 v.
ad7265 rev. a | page 6 of 28 absolute maximum ratings table 3. parameter rating v dd to agnd ?0.3 v to +7 v dv dd to dgnd ?0.3 v to +7 v v drive to dgnd ?0.3 v to dv dd v drive to agnd ?0.3 v to av dd av dd to dv dd ?0.3 v to +0.3 v agnd to dgnd ?0.3 v to +0.3 v analog input voltage to agnd ?0.3 v to av dd + 0.3 v digital input voltage to dgnd ?0.3 v to +7 v digital output voltage to gnd ?0.3 v to v drive + 0.3 v v ref to agnd ?0.3 v to av dd + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c lfcsp/tqfp ja thermal impedance 108.2c/w (lfcsp) 55c/w (tqfp) jc thermal impedance 32.71c/w (lfcsp) lead temperature, soldering reflow temperature (10 sec to 30 sec) 255c esd 1.5 kv 1 transient currents of up to 100 ma will not cause scr latch up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7265 rev. a | page 7 of 28 pin configurations and function descriptions 04674-041 cs sgl/diff 1 2 3 4 5 6 7 8 ref select av dd d cap a v a1 agnd agnd dgnd v a2 23 a2 22 21 range 18 v b1 19 agnd 20 d cap b 24 a1 17 v b2 pin 1 9 v a3 10 v a4 11 v a5 12 v a6 13 v b6 14 v b5 15 v b4 16 v b3 32 dv dd 31 v drive 30 d out a 29 dgnd 28 d out b 27 sclk 26 25 a0 ad7265 top view (not to scale) 04674-002 24 23 22 21 1 2 3 32 dv dd a0 cs sclk d out b dgnd d out a v drive 20 19 18 17 v b2 v b1 agnd d cap b range sgl/diff a2 a1 9 10 11 12 13 v b5 v b4 v b3 v b6 v a6 v a5 v a4 v a3 14 15 16 4 5 6 7 8 v a2 v a1 agnd agnd d cap a av dd ref select dgnd 31 30 29 28 27 26 25 ad7265 top view (not to scale) pin 1 indicator figure 3. 32-lead su-32-2 figure 2. 32-lead cp-32-2 table 4. pin function descriptions pin no. mnemonic description 1, 29 dgnd digital ground. this is the ground reference point for a ll digital circuitry on the ad7265. both dgnd pins should connect to the dgnd plane of a system. the dgnd and agnd voltages should ideally be at the same potential and must not be more than 0.3 v ap art, even on a transient basis. 2 ref select internal/external reference selection. logic input. if this pin is tied to dgnd, the on-chip 2.5 v reference is used as the reference source for both adc a and adc b. in addition, pin d a and pin d cap cap b must be tied to decoupling capacitors. if the ref select pin is tied to a logic high, an external reference can be supplied to the ad7265 through the d a pin and/or the d b pin. cap cap 3 av dd analog supply voltage, 2.7 v to 5.25 v. this is the only supply voltage for all analog circuitry on the ad7265. the av and dv dd dd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. this supply should be decoupled to agnd. 4, 20 d a, d b cap cap decoupling capacitor pins. decoupling capacitors (470 nf recommended) are connected to these pins to decouple the reference buffer for each respective adc. provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. the range of the external reference is dependent on the analog input range selected. 5, 6, 19 agnd analog ground. ground reference point for all analog circuitry on the ad7265. all analog input signals and any external reference signal should be referred to this ag nd voltage. all three of these agnd pins should connect to the agnd plane of a system. the agnd and dgnd voltag es ideally should be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 7 to 12 v to v a1 a6 analog inputs of adc a. these may be programmed as six single-ended channels or three true differential analog input channel pairs. see table 6 . 13 to 18 v b6 to v b1 analog inputs of adc b. these may be programmed as six single-ended channels or three true differential analog input channel pairs. see table 6 . 21 range analog input range selection. logic input. the polarity on this pin determines the input range of the analog input channels. if this pin is tied to a lo gic low, the analog input range is 0 v to v ref . if this pin is tied to a logic high when cs goes low, the analog input range is 2 v . see the analog input selection section for details. ref 22 sgl/ diff logic input. this pin selects whether the analog inputs ar e configured as differential pairs or single ended. a logic low selects differential operation while a logic high selects single-ended operation. see the analog input selection section for details. 23 to 25 a2 to a0 multiplexer select. logic inputs. these inputs are used to select the pair of channels to be simultaneously converted, such as channel 1 of both adc a and adc b, channel 2 of both adc a and adc b, and so on. the pair of channels selected may be two single-ended channels or two differential pairs. the logic states of these pins need to be set up prior to the acquisit ion time and subsequent falling edge of cs to correctly set up the multiplexer for that conversion. see the analog input selection section for further details and table 6 for multiplexer address decoding. 26 cs chip select. active low logic input. this input provides the dual function of initiating conversions on the ad7265 and framing the seri al data transfer. 27 sclk serial clock. logic input. a serial clock input provides the sclk for accessing the data from the ad7265. this clock is also used as the clock source for the conversion process.
ad7265 rev. a | page 8 of 28 pin no. mnemonic description 28, 30 d out b, d out a serial data outputs. the data output is supplied to each pin as a serial data stream. the bits are clocked out on the falling edge of the sclk input and 14 sclks are requir ed to access the data. the data simultaneously appears on both pins from the simultaneous conversions of both adcs. the data stream consists of two leading zeros followed by the 12 bits of conversion data . the data is provided msb first. if cs is held low for 16 sclk cycles rather than 14, then two trailing zeros appear after the 12 bits of data. if cs is held low for a further 16 sclk cycles on either d out a or d out b, the data from the other adc follows on the d out pin. this allows data from a simultaneous conversion on both adcs to be gathered in serial format on either d out a or d out b using only one serial port. see the serial interface section. 31 v drive logic power supply input. the voltage supplied at this pin determines at what voltage the interface operates. this pin should be decoupled to dgnd. the voltag e at this pin may be different than that at av dd and dv dd but should never exceed either by more than 0.3 v. 32 dv dd digital supply voltage, 2.7 v to 5.25 v. this is the supply voltage for all digital circuitry on the ad7265. the dv dd and av dd voltages should ideally be at the same potential and must not be more than 0.3 v apart even on a transient basis. this supply should be decoupled to dgnd.
ad7265 rev. a | page 9 of 28 typical performance characteristics t = 25c, unless otherwise noted. a 04674-003 supply ripple frequency (khz) 2000 0 200 400 600 800 1000 1200 1400 1600 1800 psrr (db) ?60 ?70 ?80 ?90 ?100 ?110 ?120 100mv p-p sine wave on av dd no decoupling single-ended mode external reference internal reference 04674-006 frequency (khz) 500 0 50 100 150 200 250 300 350 400 450 (db) ?10 ?30 ?50 ?70 ?90 ?110 4096 point fft v dd = 5v, v drive = 3v f sample = 1msps f in = 26khz sinad = 71.4db thd = ?84.42db differential mode figure 7. fft figure 4. psrr vs. supply ripple freq uency without supply decoupling 04674-007 code 4000 0 1000 2000 3000 3500 500 1500 2500 dnl error (lsb) 1.0 0.6 0.8 0.2 0.4 ?0.2 0 ?0.6 ?0.8 ?0.4 ?1.0 v dd = 5v, v drive = 3v differential mode 04674-004 noise frequency (khz) 1000 0 100 200 300 400 500 600 800700 900 isolation (db) ?50 ?55 ?60 ?65 ?70 ?75 ?90 ?95 ?80 ?85 ?100 v dd = 5v figure 8. typical dnl figure 5. channel- to-channel isolation 04674-008 code 4000 0 500 1000 1500 2000 2500 3000 3500 inl error (lsb) 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 v dd = 5v, v drive = 3v differential mode 04674-005 input frequency (khz) 1000 0 500 sinad (db) 74 72 68 70 66 v dd = 5v differential mode v dd = 3v differential mode range = 0 to v ref figure 6. sinad vs. analog input frequency for various supply voltages figure 9. typical inl
ad7265 rev. a | page 10 of 28 04674-012 code 2046 2047 2049 2048 2050 no. of occurrences 10000 8000 9000 6000 7000 4000 5000 2000 1000 3000 0 10000 codes differential mode internal reference 04674-009 v ref (v) 2.5 0 0.5 1.0 1.5 2.0 linearity error (lsb) 1.0 0.6 0.8 0.2 0.4 ?0.2 0 ?0.6 ?0.4 ?1.0 ?0.8 v dd = 3v/5v differential mode positive inl positive dnl negative dnl negative inl figure 10. linearity error vs. v figure 13. histogram of codes for 10k samples in differential mode ref 04674-010 v ref (v) 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 effective number of bits 12.0 11.0 11.5 10.0 10.5 9.0 9.5 8.0 7.5 8.5 7.0 v dd = 5v differential mode v dd = 3v differential mode v dd = 3v single-ended mode v dd = 5v single-ended mode 04674-042 code 2046 2047 2048 2049 2050 no. of occurrences 10000 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 9984 codes single-ended mode internal reference 5 codes 11 codes figure 11. effective number of bits vs. v ref figure 14. histogram of codes for 10k samples in single-ended mode 04674-011 current load ( a) 200 0 20 40 60 80 100 120 140 160 180 v ref (v) 2.5010 2.5000 2.5005 2.4995 2.4990 2.4985 2.4980 04674-040 ripple frequency (khz) 1200 0 200 400 600 800 1000 cmrr (db) ?60 ?65 ?70 ?75 ?80 ?85 ?95 ?90 ?100 differential mode v dd = 3v/5v vs. reference output current drive figure 12. v ref figure 15. cmrr vs. common-mode ripple frequency
ad7265 rev. a | page 11 of 28 terminology differential nonlinearity (dnl) signal-to-(noise + distortion) ratio (sinad) differential nonlinearity is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. sinad is the measured ratio of signal-to-(noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all non-fundamental signals up to half the sampling frequency (f integral nonlinearity (inl) s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale with a single (1) lsb point below the first code transition, and full scale with a 1 lsb point above the last code transition. signal-to- ( noise + distortion ) = (6.02n + 1.76) db therefore, for a 12-bit converter, this is 74 db. offset error offset error applies to straight binary output coding. it is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal (agnd + 1 lsb). total harmonic distortion (thd) total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. for the ad7265, it is defined as offset error match 1 2 6 2 5 2 4 2 3 2 2 log20)( v vvvvv dbthd ++++ = offset error match is the difference in offset error across all 12 channels. where: gain error gain error applies to straight binary output coding. it is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (vref ? 1 lsb) after the offset error is adjusted out. gain error does not include reference error. v is the rms amplitude of the fundamental. 1 v , v , v , v gain error match gain error match is the difference in gain error across all 12 channels. zero code error zero code error applies when using twos complement output coding with, for example, the 2 vref input range as ?vref to +vref biased about the vref point. it is the deviation of the midscale transition (all 1s to all 0s) from the ideal vin voltage (vref). zero code error match zero code error match refers to the difference in zero code error across all 12 channels. positive gain error this applies when using twos complement output coding with, for example, the 2 v ref input range as ?v ref to +v ref biased about the v ref point. it is the deviation of the last code transition (011110) to (011111) from the ideal (+v ref ? 1 lsb) after the zero code error is adjusted out. track-and-hold acquisition time the track-and-hold amplifier returns to track mode after the end of conversion. track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion. 2 3 4 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic, or spurious noise, is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is a noise peak. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a full- scale (2 v when v = 5 v , and v when v ref dd ref dd = 3 v), 10 khz sine wave signal to all unselected input channels and determining how much that signal is attenuated in the selected channel with a 50 khz signal (0 v to v ref ). the result obtained is the worst-case across all 12 channels for the ad7265. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum, and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second-order terms include (fa + fb) and (fa ? fb), while the third-order terms includ e (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb).
ad7265 rev. a | page 12 of 28 the ad7265 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. as a result, the second-order and third-order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. thermal hysteresis thermal hysteresis is defined as the absolute maximum change of reference output voltage after the device is cycled through temperature from either t_hys+ = +25c to t max to +25c or t_hys? = +25c to t min to +25c it is expressed in ppm by 6 10 )c25( )_()c25( )( ? = ref ref ref hys v hystv v ppmv common-mode rejection ratio (cmrr) cmrr is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 100 mv p-p sine wave applied to the common-mode voltage of v where: v and v in+ in? of frequency f ref (25c) is v ref at 25c. v s as ref (t_hys) is the maximum change of v ref at t_hys+ or t_hys?. cmrr (db) = 10 log( pf / p f s ) where: pf is the power at frequency f in the adc output. f p s is the power at frequency f s in the adc output. power supply rejection ratio (psrr) variations in power supply affect the full-scale transition but not the converters linearity. psrr is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see figure 4 ).
ad7265 rev. a | page 13 of 28 theory of operation when the adc starts a conversion (see figure 17 ), sw3 opens and sw1 and sw2 move to position b, causing the comparator to become unbalanced. both inputs are disconnected once the conversion begins. the control logic and the charge redistribution dacs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. the output impedances of the sources driving the v circuit information the ad7265 is a fast, micropower, dual, 12-bit, single-supply, adc that operates from a 2.7 v to a 5.25 v supply. when operated from either a 3 v or a 5 v supply, the ad7265 is capable of throughput rates of 1 msps when provided with a 16 mhz clock. the ad7265 contains two on-chip, differential track-and-hold amplifiers, two successive approximation adcs, and a serial interface with two separate data output pins. it is housed in a 32-lead lfcsp or a 32-lead tqfp, offering the user considerable space-saving advantages over alternative solutions. the serial clock input accesses data from the part, but also provides the clock source for each successive approximation adc. the analog input range for the part can be selected to be a 0 v to v and v in+ in? pins must be matched; otherwise, the two inputs will have different settling times, resulting in errors. capacitive dac capacitive dac control logic comparator sw3 sw1 a a b b sw2 c s c s v in+ v in? v ref 04674-014 input or a 2 v ref ref input, configured with either single-ended or differential analog inputs. the ad7265 has an on-chip 2.5 v reference that can be overdriven when an external reference is preferred. if the internal reference is to be used elsewhere in a system, then the output needs to be buffered first. the ad7265 also features power-down options to allow power saving between conversions. the power-down feature is implemented via the standard serial interface, as described in the figure 17. adc conversion phase analog input structure modes of operation section. figure 18 shows the equivalent circuit of the analog input structure of the ad7265 in differential/pseudo differential modes. in single-ended mode, v converter operation the ad7265 has two successive approximation adcs, each based around two capacitive dacs. in? is internally tied to agnd. the four diodes provide esd protection for the analog inputs. care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mv. this causes these diodes to become forward-biased and starts conducting into the substrate. these diodes can conduct up to 10 ma without causing irreversible damage to the part. figure 16 and figure 17 show simplified schematics of one of these adcs in acquisition and conversion phase, respectively. the adc is comprised of control logic, a sar, and two capacitive dacs. in figure 16 (the acquisition phase), sw3 is closed, sw1 and sw2 are in position a, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. the c1 capacitors in figure 18 are typically 4 pf and can primarily be attributed to pin capacitance. the resistors are lumped components made up of the on resistance of the switches. the value of these resistors is typically about 100 . the c2 capacitors are the adcs sampling capacitors with a capacitance of 45 pf typically. capacitive dac capacitive dac control logic comparator sw3 sw1 a a b b sw2 c s c s v in+ v in? v ref 04674-013 for ac applications, removing high frequency components from the analog input signal is recommended by the use of an rc low-pass filter on the relevant analog input pins with optimum values of 47 and 10 pf. in applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc and may necessitate the use of an input buffer amplifier. the choice of the op amp is a function of the particular application. figure 16. adc acquisition phase
ad7265 rev. a | page 14 of 28 v dd c1 d d v in+ r1 c2 v dd c1 d d v in? r1 c2 04674-015 figure 21 shows a graph of the thd vs. the analog input frequency for various supplies while sampling at 1 msps. in this case, the source impedance is 47 . 04674-018 input frequency (khz) 600 0 200 100 400 300 500 thd (db) ?50 ?60 ?55 ?65 ?70 ?75 ?80 ?85 ?90 v dd = 3v single-ended mode v dd = 5v single-ended mode v dd = 3v differential mode v dd = 5v differential mode f sample = 1msps v dd = 3v/5v range = 0 to v ref figure 18. equivalent analog input circuit, conversion phaseswitches open, track phaseswitches closed when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance depends on the amount of thd that can be toler- ated. the thd increases as the source impedance increases and performance degrades. figure 21. thd vs. analog input frequency for various supply voltages figure 19 shows a graph of the thd vs. the analog input signal frequency for different source impedances in single-ended mode, while analog inputs figure 20 shows the thd vs. the analog input signal frequency for different source impedances in differential mode. the ad7265 has a total of 12 analog inputs. each on-board adc has six analog inputs that can be configured as six single- ended channels, three pseudo differential channels, or three fully differential channels. these can be selected as described in the 04674-016 input frequency (khz) 600 02 0 0 100 400 300 500 thd (db) ?50 ?60 ?55 ?65 ?70 ?75 ?80 ?85 ?90 f sample = 1msps v dd = 3v range = 0v to v ref r source = 0 ? r source = 10 ? r source = 47 ? r source = 100 ? r source = 300 ? analog input selection section. single-ended mode the ad7265 can have a total of 12 single-ended analog input channels. in applications where the signal source has high impedance, it is recommended to buffer the analog input before applying it to the adc. the analog input range can be pro- grammed to be either 0 to v or 0 to 2 v . ref ref if the analog input signal to be sampled is bipolar, the internal reference of the adc can be used to externally bias up this signal to make it correctly formatted for the adc. figure 22 shows a typical connection diagram when operating the adc in single-ended mode. figure 19. thd vs. analog input frequency for various source impedances, single-ended mode v in 0v +1.25v ?1.25v d cap a/d cap b v a1 v b6 r r 3r r 0v +2.5 v 0.47f 1 additional pins omitted for clarity. 04674-019 ad7265 1 04674-017 input frequency (khz) 600 02 0 0 100 400 300 500 thd (db) ? 60 ?65 ?70 ?75 ?80 ?85 ?90 f sample = 1msps v dd = 3v range = 0v to v ref r source = 300 ? r source = 0 ? r source = 10 ? r source = 47 ? r source = 100 ? figure 22. single-ended mode connection diagram figure 20. thd vs. analog input frequency for various source impedances, differential mode
ad7265 rev. a | page 15 of 28 04674-021 v ref (v) 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 common-mode range (v) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 t a = 25c differential mode the ad7265 can have a total of six differential analog input pairs. differential signals have some benefits over single-ended signals, including noise immunity based on the devices common-mode rejection and improvements in distortion performance. figure 23 defines the fully differential analog input of the ad7265. v in+ v in? v ref p-p v ref p-p common mode voltage 1 additional pins omitted for clarity. 04674-020 ad7265 1 figure 24. input common-mode range vs. v (0 to v range, v figure 23. differential input definition the amplitude of the differential signal is the difference between the signals applied to the v in+ and v in? pins in each differential pair (v in+ ? v in? ). v in+ and v in? should be simultaneously driven by two signals each of amplitude v ref (or 2 v ref , depending on the range chosen) that are 180 out of phase. the amplitude of the differential signal is therefore (assuming the 0 to v ref range is selected) ?v ref to +v ref peak- to-peak (2 v ref ), regardless of the common mode (cm). the common mode is the average of the two signals (v in+ + v in? )/2 and is therefore the voltage on which the two inputs are centered. this results in the span of each input being cm v ref /2. this voltage has to be set up externally, and its range varies with the reference value, v ref . as the value of v ref increases, the common- mode range decreases. when driving the inputs with an amplifier, the actual common-mode range is determined by the amplifiers output voltage swing. figure 24 and figure 25 show how the common-mode range typically varies with v ref for a 5 v power supply using the 0 to v ref range or 2 v ref range, respectively. the common mode must be in this range to guarantee the functionality of the ad7265. when a conversion takes place, the common mode is rejected, resulting in a virtually noise-free signal of amplitude ?v ref to +v ref corresponding to the digital codes of 0 to 4096. if the 2 v ref range is used, then the input signal amplitude extends from ?2 v ref to +2 v ref after conversion. ref ref dd = 5 v) 04674-022 v ref (v) 2.5 0 0.5 1.0 1.5 2.0 common-mode range (v) 5.0 4.0 4.5 3.0 3.5 2.0 2.5 0.5 1.0 1.5 0 t a = 25c figure 25. input common-mode range vs. v (2 v range, v ref ref dd = 5 v) driving differential inputs differential operation requires that v and v in+ in? be simultaneously driven with two equal signals that are 180 out of phase. the common mode must be set up externally. the common-mode range is determined by v ref , the power supply, and the particular amplifier used to drive the analog inputs. differential modes of operation with either an ac or dc input provide the best thd performance over a wide frequency range. because not all applications have a signal preconditioned for differential operation, there is often a need to perform single-ended-to-differential conversion.
ad7265 rev. a | page 16 of 28 using an op amp pair pseudo differential mode an op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the ad7265. the circuit configurations illustrated in the ad7265 can have a total of six pseudo differential pairs. in this mode, v in+ is connected to the signal source that must have an amplitude of v figure 26 and figure 27 show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively. (or 2 v ref ref , depending on the range chosen) to make use of the full dynamic range of the part. a dc input is applied to the v in? pin. the voltage applied to this input provides an offset from ground or a pseudo ground for the v in+ input. the benefit of pseudo differential inputs is that they separate the analog input signal ground from the adcs ground allowing dc common-mode voltages to be cancelled. the typical voltage range for the v the voltage applied to point a sets up the common-mode voltage. in both diagrams, it is connected in some way to the reference, but any value in the common-mode range can be input here to set up the common mode. the ad8022 is a suitable dual op amp that can be used in this configuration to provide differential drive to the ad7265. in? pin, while in pseudo differential mode, is shown in figure 28 and figure 29 . figure 30 shows a connection diagram for pseudo differential mode. 04674-043 v ref (v) 3.0 0 0.5 1.0 1.5 2.0 2.5 v in? (v) 1.0 0.8 0.4 0.6 0.2 ?0.2 0 ?0.4 t a = 25c take care when choosing the op amp; the selection depends on the required power supply and system performance objectives. the driver circuits in figure 26 and figure 27 are optimized for dc coupling applications requiring best distortion performance. the circuit configuration shown in figure 26 converts a unipolar, single-ended signal into a differential signal. the differential op amp driver circuit shown in figure 27 is configured to convert and level shift a single-ended, ground- referenced (bipolar) signal to a differential signal centered at the v level of the adc. ref gnd 2 v ref p-p 27 ? 27 ? v+ v? v+ v? v ref 2.5v 3.75v 1.25v 2.5v 3.75v 1.25v d cap a/d cap b v in+ v in? 440 ? 220 ? 0.47f 1 additional pins omitted for clarity. 220 ? 220 ? 10k ? a 04674-023 ad7265 1 figure 28. v in? input voltage range vs. v ref in pseudo differentia l mode with v dd = 3 v 04674-044 v ref (v) 5.0 0 0.51.01.52.02.53.03.54.04.5 v in? (v) 2.5 2.0 1.5 1.0 0.5 0 ?0.5 t a = 25c figure 26. dual op amp circuit to convert a single-ended unipolar signal into a differential signal 20k ? 220k ? 2 v ref p-p 27 ? 27 ? v+ v? v+ v? gnd 2.5v 3.75v 1.25v 2.5v 3.75v 1.25v d cap a/d cap b v in+ v in? 440 ? 220 ? 0.47f 1 additional pins omitted for clarity. 220 ? 220 ? 10k ? a 04674-024 ad7265 1 figure 29. v in? input voltage range vs. v ref in pseudo differentia l mode with v dd = 5 v dc input voltage v ref p?p v ref v in+ v in? 0.47f 1 additional pins omitted for clarity. 04674-025 ad7265 1 figure 27. dual op amp circuit to convert a single-ended bipolar signal into a differential unipolar signal figure 30. pseudo different ial mode connection diagram
ad7265 rev. a | page 17 of 28 the channels used for simultaneous conversions are selected via the multiplexer address input pins, a0 to a2. the logic states of these pins also need to be established prior to the acquisition time; however, they may change during the conversion time, provided that the mode is not changed. if the mode is changed from fully differential to pseudo-differential, for example, then the acquisition time would start again from this point. the selected input channels are decoded as shown in analog input selection the analog inputs of the ad7265 can be configured as single- ended or true differential via the sgl/ diff logic pin, as shown in figure 31 . if this pin is tied to a logic low, the analog input channels to each on-chip adc are set up as three true differen- tial pairs. if this pin is at logic high, the analog input channels to each on-chip adc are set up as six single-ended analog inputs. the required logic level on this pin needs to be established prior to the acquisition time and remain unchanged during the con- version time until the track-and-hold has returned to track. the track-and-hold returns to track on the 13 table 6 . the analog input range of the ad7265 can be selected as 0 v to v or 0 v to 2 v ref ref via the range pin. this selection is made in a similar fashion to that of the sgl/ diff pin by setting the logic state of the range pin a time t th rising edge of sclk after the cs falling edge (see figure 41 ). if the level on this pin is changed, it is recognized by the ad7265; therefore, it is necessary to keep the same logic level during acquisition and conversion to avoid corrupting the conversion in progress. acq prior to the falling edge of cs . subsequent to this, the logic level on this pin can be altered after the third falling edge of sclk. if this pin is tied to a logic low, the analog input range selected is 0 v to v ref . if this pin is tied to a logic high, the analog input range selected is 0 v to 2 v diff for example, in figure 31 , the sgl/ pin is set at logic high for the duration of both the acquisition and conversion times so the analog inputs are configured as single ended for that conversion (sampling point a). the logic level of the sgl/ ref . output coding diff changed to low after the track-and-hold returned to track and prior to the required acquisition time for the next sampling instant at point b; therefore, the analog inputs are configured as differential for that conversion. the ad7265 output coding is set to either twos complement or straight binary, depending on which analog input configuration is selected for a conversion. table 5 shows which output coding scheme is used for each possible analog input configuration. table 5. ad7265 output coding sclk cs 11 4 1 4 1 a sgl/diff b t acq 04674-026 figure 31. selecting differential or single-ended configuration sgl/ diff range output coding diff 0 v to v twos complement ref diff 0 v to 2 v ref twos complement sgl 0 v to v ref straight binary sgl 0 v to 2 v ref twos complement pseudo diff 0 v to v ref straight binary pseudo diff 0 v to 2 v twos complement ref table 6. analog input type and channel selection adc a adc b sgl/ diff v v v a2 a1 a0 v in+ in? in+ in? comment 1 0 0 0 v agnd v agnd single ended a1 b1 1 0 0 1 v agnd v agnd a2 b2 single ended 1 0 1 0 v agnd v agnd a3 b3 single ended 1 0 1 1 v agnd v agnd a4 b4 single ended 1 1 0 0 v agnd v agnd a5 b5 single ended 1 1 0 1 v agnd v agnd a6 b6 single ended 0 0 0 0 v v v a1 a2 b1 v b2 fully differential 0 0 0 1 v v v v a1 a2 b1 b2 pseudo differential 0 0 1 0 v v v a3 a4 b3 v b4 fully differential 0 0 1 1 v v v v a3 a4 b3 b4 pseudo differential 0 1 0 0 v v v a5 a6 b5 v b6 fully differential 0 1 0 1 v v v v pseudo differential a5 a6 b5 b6
ad7265 rev. a | page 18 of 28 transfer functions digital inputs the designed code transitions occur at successive integer lsb values (1 lsb, 2 lsb, and so on). in single-ended mode, the lsb size is v the digital inputs applied to the ad7265 are not limited by the maximum ratings that limit the analog inputs. instead, the digital inputs can be applied up to 7 v and are not restricted by the v /4096 when the 0 v to v ref ref range is used, and the lsb size is 2 v /4096 when the 0 v to 2 v ref ref range is used. in differential mode, the lsb size is 2 v + 0.3 v limit, as are the analog inputs. see the dd absolute maximum ratings ref /4096 when the 0 v to v section for more information. another advantage of the sclk, range, a0 to a2, and ref range is used, and the lsb size is 4 v ref /4096 when the 0 v to 2 v cs pins not being restricted by the v ref range is used. the ideal transfer characteristic for the ad7265 when straight binary coding is output is shown in dd + 0.3 v limit is that power supply sequencing issues are avoided. if one of these digital inputs is applied before v figure 32 , and the ideal transfer characteristic for the ad7265 when twos complement coding is output is shown (with the 2 v dd , there is no risk of latch-up, as there would be on the analog inputs if a signal greater than 0.3 v were applied prior to v range) in figure 33 . ref dd . 04674-027 000...000 111...111 1lsb = v ref /4096 1lsb v ref ? 1lsb analog input adc code 0v 000...001 000...010 111...110 111...000 011...111 note 1. v ref is either v ref or 2 v ref . v drive the ad7265 also has a v drive feature to control the voltage at which the serial interface operates. v drive allows the adc to easily interface to both 3 v and 5 v processors. for example, if the ad7265 was operated with a v of 5 v, the v dd drive pin could be powered from a 3 v supply, allowing a large dynamic range with low voltage digital processors. therefore, the ad7265 could be used with the 2 v input range, with a v ref dd of 5 v while still being able to interface to 3 v digital parts. figure 32. straight binary transfer characteristic 04674-028 100...000 011...111 1lsb = 2 v ref /4096 +v ref ? 1 lsb ?v ref + 1lsb v ref ? 1lsb analog input adc code 100...001 100...010 011...110 000...001 000...000 111...111 figure 33. twos complement transfer characteristic with v v input range ref ref
ad7265 rev. a | page 19 of 28 modes of operation once 32 sclk cycles have elapsed, the d the mode of operation of the ad7265 is selected by controlling the (logic) state of the out line returns to three-state on the 32 cs signal during a conversion. there are three possible modes of operation: normal mode, partial power- down mode, and full power-down mode. after a conversion is initiated, the point at which cs sclk falling edge. if nd is brought high prior to this, the d out line returns to three-state at that point. therefore, cs may idle low after 32 sclk cycles until it is brought high again sometime prior to the next conversion (effectively idling cs is pulled high determines which power-down mode, if any, the device enters. similarly, if already in a power-down mode, cs low), if so desired, because the bus still returns to three-state upon completion of the dual result read. cs can control whether the device returns to normal operation or remains in power-down. these modes of operation are designed to provide flexible power management options. these options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. once a data transfer is complete and d a and d out out b have returned to three-state, another conversion can be initiated after the quiet time, t cs normal mode this mode is intended for applications that need the fastest throughput rates because the user does not have to worry about any power-up times with the ad7265 remaining fully powered at all times. figure 34 shows the general diagram of the operation of the ad7265 in this mode. sclk leading zeros + conversion result cs d out a d out b 1 10 1 4 04674-029 figure 34. normal mode operation the conversion is initiated on the falling edge of cs , as described in the serial interface section. to ensure that the part remains fully powered up at all times, cs must remain low until at least 10 sclk falling edges have elapsed after the falling edge of cs . if cs is brought high any time after the 10 th sclk falling edge but before the 14 th sclk falling edge, the part remains powered up, but the conversion is terminated and d out a and d out b go back into three-state. fourteen serial clock cycles are required to complete the conversion and access the conversion result. the d out line does not return to three-state after 14 sclk cycles have elapsed, but instead does so when cs is brought high again. if cs is left low for another 2 sclk cycles (for example, if only a 16 sclk burst is available), two trailing zeros are clocked out after the data. if cs is left low for a further 14 (or 16) sclk cycles, the result from the other adc on board is also accessed on the same d out line, as shown in figure 42 (see the serial interface section). quiet , has elapsed by bringing low again (assuming the required acquisition time is allowed). partial power-down mode this mode is intended for use in applications where slower throughput rates are required. either the adc is powered down between each conversion, or a series of conversions may be performed at a high throughput rate, and the adc is then powered down for a relatively long duration between these bursts of several conversions. when the ad7265 is in partial power-down, all analog circuitry is powered down except for the on-chip reference and reference buffer. to enter partial power-down mode, the conversion process must be interrupted by bringing cs high anywhere after the second falling edge of sclk and before the 10 th falling edge of sclk, as shown in cs figure 35 . once is brought high in this window of sclks, the part enters partial power-down, the conversion that was initiated by the falling edge of cs is terminated, and d out a and d b go back into three-state. if out cs is brought high before the second sclk falling edge, the part remains in normal mode and does not power down. this avoids accidental power-down due to glitches on the cs line. sclk three-state cs d out a d out b 11 10 4 2 04674-030 figure 35. entering partial power-down mode
ad7265 rev. a | page 20 of 28 to exit this mode of operation and power up the ad7265 again, a dummy conversion is performed. on the falling edge of cs , the device begins to power up and continues to power up as long as cs is held low until after the falling edge of the 10 th sclk. the device is fully powered up after approximately 1 s has elapsed, and valid data results from the next conversion, as shown in figure 36 . if cs is brought high before the second falling edge of sclk, the ad7265 again goes into partial power-down. this avoids accidental power-up due to glitches on the cs line. although the device may begin to power up on the falling edge of cs , it powers down again on the rising edge of cs . if the ad7265 is already in partial power-down mode and cs is brought high between the second and 10 th falling edges of sclk, the device enters full power-down mode. full power-down mode this mode is intended for use in applications where throughput rates slower than those in the partial power-down mode are required, as power-up from a full power-down takes substantially longer than that from partial power-down. this mode is more suited to applications where a series of conversions performed at a relatively high throughput rate are followed by a long period of inactivity and thus power-down. when the ad7265 is in full powe r-down, all analog circuitry is powered down. full power-down is entered in a similar way as partial power-down, except the timing sequence shown in figure 35 must be executed twice. the conversion process must be interrupted in a similar fashion by bringing cs high anywhere after the second falling edge of sclk and before the 10 th falling edge of sclk. the device enters partial power-down at this point. to reach full power-down, the next conversion cycle must be interrupted in the same way, as shown in figure 37 . once cs is brought high in this window of sclks, the part completely powers down. cs note that it is not necessary to complete the 14 sclks once is brought high to enter a power-down mode. to exit full power-down and power up the ad7265, a dummy conversion is performed, as when powering up from partial power-down. on the falling edge of cs , the device begins to power up and continues to power up, as long as cs is held low until after the falling edge of the 10 th sclk. the required power-up time must elapse before a conversion can be initiated, as shown in figure 38 . see the power-up times section for the power-up times associated with the ad7265. sclk cs d out a d out b invalid data valid data 11 0 1 4 1 4 1 the part begins to power up. the part is fully powered up; see power-up times section. t power-up1 04674-031 figure 36. exiting partial power-down mode three-state 11 0 1 4 2 sclk cs d out a d out b three-state 11 0 2 invalid data invalid data the part begins to power up. the part enters partial power down. the part enters full power down. 04674-032 1 4 figure 37. entering full power-down mode
ad7265 rev. a | page 21 of 28 sclk d out a d out b invalid data valid data 1 10 14 14 1 the part begins to power up. the part is fully powered up, see power-up times section. t power-up2 cs 04674-033 figure 38. exiting full power-down mode power-up times as described in detail, the ad7265 has two power-down modes, partial power-down and full power-down. this section deals with the power-up time required when coming out of either of these modes. it should be noted that the power-up times, as explained in this section, apply with the recommended capacitors in place on the d cap a and d cap b pins. to power up from full power-down (whether using an internal or external reference), approximately 1.5 ms should be allowed from the falling edge of cs , shown as t power-up2 in figure 38 . powering up from partial power-down requires much less time. the power-up time from partial power-down is typically 1 s; however, if using the internal reference, then the ad7265 must be in partial power-down for at least 67 s in order for this power-up time to apply. when power supplies are first applied to the ad7265, the adc may power up in either of the power-down modes or normal mode. because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. likewise, if it is intended to keep the part in the partial power-down mode immediately after the supplies are applied, then two dummy cycles must be initiated. the first dummy cycle must hold cs low until after the 10 th sclk falling edge (see figure 34 ); in the second cycle, cs must be brought high before the 10 th sclk edge but after the second sclk falling edge (see figure 35 ). alternatively, if it is intended to place the part in full power-down mode when the supplies are applied, then three dummy cycles must be initiated. the first dummy cycle must hold cs low until after the 10 th sclk falling edge (see figure 34 ); the second and third dummy cycles place the part in full power-down (see figure 37 ). once supplies are applied to the ad7265, enough time must be allowed for any external reference to power up and charge the various reference buffer decoupling capacitors to their final values. power vs. throughput rate the power consumption of the ad7265 varies with throughput rate. when using very slow throughput rates and as fast an sclk frequency as possible, the various power-down options can be used to make significant power savings. however, the ad7265 quiescent current is low enough that even without using the power-down options, there is a noticeable variation in power consumption with sampling rate. this is true whether a fixed sclk value is used or if it is scaled with the sampling rate. figure 39 and figure 40 show plots of power vs. the throughput rate when operating in normal mode for a fixed maximum sclk frequency, and an sclk frequency that scales with the sampling rate with v dd = 3 v and v dd = 5 v, respectively. in all cases, the internal reference was used. 04674-045 throughput (ksps) 1000 0 100 200 300 500400 700 800 900 600 power (mw) 10.0 9.0 8.5 9.5 8.0 7.0 6.5 7.5 6.0 5.5 5.0 16mhz sclk variable sclk t a = 25c figure 39. power vs. throughp ut in normal mode with v dd = 3 v 04674-046 throughput (ksps) 1000 0 200 300 400 100 500 600 700 800 900 power (mw) 25 21 19 23 17 13 15 9 7 11 5 variable sclk t a = 25c 16mhz sclk figure 40. power vs. throughput in normal mode with v dd = 5 v
ad7265 rev. a | page 22 of 28 serial interface a minimum of 14 serial clock cycles are required to perform the conversion process and to access data from one conversion on either data line of the ad7265. figure 41 shows the detailed timing diagram for serial inter- facing to the ad7265. the serial clock provides the conversion clock and controls the transfer of information from the ad7265 during conversion. cs going low provides the leading zero to be read in by the microcontroller or dsp. the remaining data is then clocked out by subsequent sclk falling edges, beginning with a second leading zero. therefore, the first falling clock edge on the serial clock has the leading zero pro- vided and also clocks out the second leading zero. the 12-bit result then follows with the final bit in the data transfer valid on the 14 cs the signal initiates the data tran sfer and conversion process. the falling edge of cs puts the track-and-hold into hold mode, at which point the analog input is sampled and the bus is taken out of three-state. the conversion is also initiated at this point and requires a minimum of 14 sclks to complete. once 13 sclk falling edges have elapsed, the track-and-hold goes back into track on the next sclk rising edge, as shown in th falling edge, having being clocked out on the previous (13 th ) falling edge. it may also be possible to read in data on each sclk rising edge depend ing on the sclk frequency or the supply voltage. the first rising edge of sclk after the figure 41 at point b. if a 16-sclk transfer is used, then two trailing zeros will appear after the final lsb. on the rising edge of cs falling edge would have the second leading zero provided, and the 13 cs , the conversion is terminated and d out a and d out b go back into three-state. if th rising sclk edge would have db0 provided. cs is not brought high but is instead held low for a further 14 (or 16) sclk cycles on d note that with fast sclk values, and thus short sclk periods, in order to allow adequately for t out a, the data from con- version b is output on d out a (followed by 2 trailing zeros). 2 , an sclk rising edge may occur before the first sclk falli ng edge. this rising edge of sclk can be ignored for the purposes of the timing descriptions in this section. if a falling edge of sclk is coincident with the falling edge of cs likewise, if is held low for a further 14 (or 16) sclk cycles on d b, the data from conversion a is output on d out out b. this is illustrated in figure 42 where the case for d out a is shown. in this case, the d cs , then this falling ed ge of sclk is not acknowledged by the ad7265, and the next falling edge of sclk will be the first registered after the falling edge of out line in use goes back into three-state on the 32 nd sclk falling edge or the rising edge of cs , whichever occurs first. cs . cs sclk 1 5 13 d out a d out b 2 leading zeros three- state t 4 2 34 t 5 t 3 t quiet t 2 three-state db11 db10 db2 db0 t 6 t 7 t 8 0 0 db1 b db9 db8 t 9 04674-034 figure 41. serial interface timing diagram cs sclk 1 5 15 d out a three- state t 4 2 34 16 t 5 t 3 t 2 three- state t 6 t 7 14 zero0 zero db11 b 17 2 leading zeros t 10 32 db11 a 2 leading zeros db10 a db9 a zero zero zero 2 trailing zeros zero zero 2 trailing zeros 04674-035 figure 42. reading data from both adcs on one d line with 32 sclks out
ad7265 rev. a | page 23 of 28 microprocessor interfacing the connection diagram is shown in the serial interface on the ad7265 allows the part to be directly connected to a range of many different microprocessors. this section explains how to interface the ad7265 with some of the more common microcontroller and dsp serial interface protocols. figure 43 . the adsp-218x has the tfs0 and rfs0 of the sport0 and the rfs1 of sport1 tied together. tfs0 is set as an output, and both rfs0 and rfs1 are set as inputs. the dsp operates in alternate framing mode, and the sport control register is set up as described. the frame synchronization signal generated on the tfs is tied to ad7265 to adsp-218x cs , and, as with all signal processing applications, equidistant sampling is necessary. however, in this example, the timer interrupt is used to control the sampling rate of the adc and, under certain conditions, equidistant sampling may not be achieved. the adsp-218x family of dsps interface directly to the ad7265 without any glue logic required. the v drive pin of the ad7265 takes the same supply voltage as that of the adsp- 218x. this allows the adc to operate at a higher supply voltage than its serial interface and, therefore, the adsp-218x, if necessary. this example shows both d ad7265 1 sclk cs adsp-218x 1 1 additional pins omitted for clarity. sclk0 dr0 rfs0 tfs0 d out a v drive v dd d out b dr1 rfs1 sclk1 04674-036 a and d out out b of the ad7265 connected to both serial ports of the adsp-218x. the sport0 and sport1 control registers should be set up as shown in table 7 and table 8 . table 7. sport0 control register setup setting description tfsw = rfsw = 1 alternate framing invrfs = invtfs = 1 active low frame signal dtype = 00 right justify data slen = 1111 16-bit data-word (or may be set to 1101 for 14-bit data-word) isclk = 1 internal serial clock tfsr = rfsr = 1 frame every word figure 43. interfacing the ad7265 to the adsp-218x irfs = 0 itfs = 1 the timer registers are loaded with a value that provides an interrupt at the required sample interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to control the rfs, and hence, the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given (ax0 = tx0), the state of the sclk is checked. the dsp waits until the sclk has gone high, low, and high again before transmission starts. if the timer and sclk values are chosen such that the instruction to transmit occurs on or near the rising edge of sclk, then the data may be transmitted or it may wait until the next clock edge. table 8. sport1 control register setup setting description tfsw = rfsw = 1 alternate framing invrfs = invtfs = 1 active low frame signal dtype = 00 right justify data slen = 1111 16-bit data-word (or may be set to 1101 for 14-bit data-word) isclk = 0 external serial clock tfsr = rfsr = 1 frame every word irfs = 0 itfs = 1 for example, the adsp-2111 has a master clock frequency of 16 mhz. if the sclkdiv register is loaded with the value 3, then an sclk of 2 mhz is obtained, and eight master clock periods will elapse for every one sclk period. if the timer registers are loaded with the value 803, then 100.5 sclks will occur between interrupts and, subsequently, between transmit instructions. this situation yields sampling that is not equidistant, as the transmit instruction is occurring on a sclk edge. if the number of sclks between interrupts is a whole integer figure of n, then equidistant sampling will be implemented by the dsp. to implement the power-down modes, slen should be set to 1001 to issue an 8-bit sclk burst.
ad7265 rev. a | page 24 of 28 ad7265 to adsp-bf53x ad7265 to tms320c541 the adsp-bf53x family of dsps interface directly to the ad7265 without any glue logic required. the availability of secondary receive registers on the serial ports of the blackfin? dsps means only one serial port is necessary to read from both d the serial interface on the tms320c541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the ad7265. the cs input allows easy interfacing between the tms320c541 and the ad7265 without any glue logic required. the serial ports of the tms320c541 are set up to operate in burst mode with internal clkx0 (tx serial clock on serial port 0) and fsx0 (tx frame sync from serial port 0). the serial port control registers (spc) must have the following setup. out pins simultaneously. figure 44 shows both d out a and d out b of the ad7265 connected to serial port 0 of the adsp-bf53x. the sport0 receive configuration 1 register and sport0 receive configuration 2 register should be set up as outlined in table 9 and table 10 . serial device a (primary) serial device b (secondary) d out a cs sclk adsp-bf53x 1 1 additional pins omitted for clarity. dr0pri dr0sec rfs0 v drive v dd d out b rclk0 04674-037 sport0 ad7265 1 table 11. serial port control register setup spc fo fsm mcm txm spc0 0 1 1 1 spc1 0 1 0 0 the format bit, fo, may be set to 1 to set the word length to 8 bits to implement the power-down modes on the ad7265. the connection diagram is shown in figure 45 . for signal processing applications, it is imperative that the frame synchronization signal from the tms320c541 provide equidistant sampling. the v drive pin of the ad7265 takes the same supply voltage as that of the tms320c541. this allows the adc to operate at a higher voltage than its serial interface, and therefore, the tms320c541, if necessary. figure 44. interfacing the ad7265 to the adsp-bf53x table 9. the sport0 receive configuration 1 register (sport0_rcr1) setting description fsr1 fsr0 sclk tms320c541 1 1 additional pins omitted for clarity. clkx0 dr1 clkr1 clkx1 d out b d out a v drive v dd cs fsx0 dr0 clkr0 04674-038 ad7265 1 rckfe = 1 sample data with falling edge of rsclk lrfs = 1 active low frame signal rfsr = 1 frame every word irfs = 1 internal rfs used rlsbit = 0 receive msb first rdtype = 00 zero fill irclk = 1 internal receive clock rspen = 1 receive enabled 16-bit data-word (or may be set to 1101 for 14-bit data-word) slen = 1111 tfsr = rfsr = 1 table 10. the sport0 receive configuration 2 register (sport0_rcr2) figure 45. interfacing the ad7265 to the tms320c541 setting description rxse = 1 secondary side enabled slen = 1111 16-bit data-word (or may be set to 1101 for 14-bit data-word) to implement the power-down modes, slen should be set to 1001 to issue an 8-bit sclk burst. a blackfin driver for the ad7265 is available to download at www.analog.com .
ad7265 rev. a | page 25 of 28 in the example shown in figure 46 , the serial clock is taken from the essi0 so the sck0 pin must be set as an output, sckd = 1, while the sck1 pin is set as an input, sckd = 0. the frame sync signal is taken from sc02 on essi0, so scd2 = 1, while on essi1, scd2 = 0; therefore, sc12 is configured as an input. the v ad7265 to dsp563xx the connection diagram in figure 46 shows how the ad7265 can be connected to the essi (synchronous serial interface) of the dsp563xx family of dsps from motorola. there are two on-board essis, and each operates in synchronous mode (bit syn = 1 in crb register) with internally generated word length frame sync for both tx and rx (bit fsl1 = 0 and bit fsl0 = 0 in crb). drive pin of the ad7265 takes the same supply voltage as that of the dsp563xx. this allows the adc to operate at a higher voltage than its serial interface and therefore the dsp563xx, if necessary. normal operation of the essi is selected by making mod = 0 in the crb. set the word length to 16 by setting bit wl1 = 1 and bit wl0 = 0 in cra. sclk dsp563xx 1 1 additional pins omitted for clarity. sck0 sc12 srd1 srd0 cs d out a d out b v drive v dd sc02 sck1 04674-039 ad7265 1 to implement the power-down modes on the ad7265, the word length can be changed to 8 bits by setting bit wl1 = 0 and bit wl0 = 0 in cra. the fsp bit in the crb should be set to 1 so the frame sync is negative. it is imperative for signal processing applications that the frame synchronization signal from the dsp563xx provides equidistant sampling. figure 46. interfacing the ad7265 to the dsp563xx
ad7265 rev. a | page 26 of 28 application hints grounding and layout the analog and digital supplies to the ad7265 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the printed circuit board (pcb) that houses the ad7265 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this design facilitates the use of ground planes that can be easily separated. to provide optimum shielding for ground planes, a minimum etch technique is generally best. all three agnd pins of the ad7265 should be sunk in the agnd plane. digital and analog ground planes should be joined in only one place. if the ad7265 is in a system where multiple devices require an agnd to dgnd connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the ground pins on the ad7265. avoid running digital lines under the device as this couples noise onto the die. however, the analog ground plane should be allowed to run under the ad7265 to avoid noise coupling. the power supply lines to the ad7265 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. to avoid radiating noise to other sections of the board, fast switching signals, such as clocks, should be shielded with digital ground, and clock signals should never run near the analog inputs. avoid crossover of digital and analog signals. to reduce the effects of feedthrough within the board, traces on opposite sides of the board should run at right angles to each other. a microstrip technique is the best method but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. the 0.1 f capacitors should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types or surface-mount types. these low esr and esi capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. pcb design guidelines for lfcsp the lands on the chip scale package (cp-32-3) are rectangular. the pcb pad for these should be 0.1 mm longer than the package land length, and 0.05 mm wider than the package land width, thereby having a portion of the pad exposed. to ensure that the solder joint size is maximized, the land should be centered on the pad. the bottom of the chip scale package has a thermal pad. the thermal pad on the pcb should be at least as large as the exposed pad. on the pcb, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. to improve thermal performance of the package, use thermal vias on the pcb incorporating them in the thermal pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. the user should connect the pcb thermal pad to agnd. evaluating the ad7265 performance the recommended layout for the ad7265 is outlined in the evaluation board documentation. the evaluation board package includes a fully assembled and tested evaluation board, docu- mentation, and software for controlling the board from the pc via the evaluation board controller. the evaluation board con- troller can be used in conjunction with the ad7265 evaluation board, as well as many other analog devices, inc. evaluation boards ending in the cb designator, to demonstrate/evaluate the ac and dc performance of the ad7265. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad7265. the software and documentation are on a cd shipped with the evaluation board.
ad7265 rev. a | page 27 of 28 outline dimensions compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) figure 47. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters compliant to jedec standards ms-026aba 0.45 0.37 0.30 0.80 bsc lead pitch 7.00 bsc sq 9.00 bsc sq 1 24 25 32 8 9 17 16 1.20 max 0.75 0.60 0.45 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity seating plane 0 min 7 3.5 0 0.15 0.05 view a rotated 90 ccw view a pin 1 top view (pins down) figure 48. 32-lead thin plastic quad flat package [tqfp] (su-32-2) dimensions shown in millimeters ordering guide model temperature range package description package option ad7265bcp C40c to +125c 32-lead lfcsp_vq cp-32-2 AD7265BCPZ C40c to +125c 32-lead lfcsp_vq cp-32-2 1 AD7265BCPZ-reel7 C40c to +125c 32-lead lfcsp_vq cp-32-2 1 AD7265BCPZ-reel C40c to +125c 32-lead lfcsp_vq cp-32-2 1 ad7265bsuz C40c to +125c 32-lead tqfp su-32-2 1 ad7265bsuz-reel7 C40c to +125c 32-lead tqfp su-32-2 1 ad7265bsuz-reel C40c to +125c 32-lead tqfp su-32-2 1 eval-ad7265cb evaluation board 2 eval-control brd2 control board 3 1 z = pb-free part. 2 this can be used as a standalone evaluation board or in conjunction with the eval-control board for evaluation/demonstration p urposes. 3 this board is a complete unit allowing a pc to control and communicate with all analog devices, inc. evaluation boards ending in the cb designators. to order a complete evaluation kit, the pa rticular adc evaluation board (s uch as, eval-ad7265cb), the eval-c ontrol brd2, and a 12 v transf ormer must be ordered. see the relevant evaluation board technical note for more information.
ad7265 rev. a | page 28 of 28 t notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04674-0-11/06(a) ttt

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